The present invention relates generally to a method for shaping a laminate substrate and more particularly to a method for shaping a laminate substrate prior to chip join.
High production flip chip organic composite laminate substrates are multi layer structures consisting of alternating layers of conductive metallurgy and dielectric. Dielectric layers may be particle filled organic dielectric (build-up layers) or particle and glass fiber filled organic dielectic (core). Laminate substrates may have length and width in the range of 20 mm to 75 mm, while thickness varies in the range of 0.3 mm to 3 mm. Individual build-up layer thicknesses are in the range of 15 um for copper, 33 um for build-up dielectric and 100 um to 1 mm for core. Laminate substrates have typical build-up dielectric coefficient of thermal expansion (CTE) values of 46 ppm/degree C., and core CTE values of 15 ppm/degree C. Next-generation materials have typical build-up dielectric CTE values of 20 ppm/degree C. and core CTE values of 12 ppm/degree C. Copper material used in composite laminate substrate fabrication is considered to have a CTE value of approximately 17 ppm over the temperature range of interest. Composite CTEs of laminate substrates are in the range of 15 ppm to 20 ppm. Room temperature dielectric loss tangent values of next generation laminate substrate materials are approx. 0.007, which are superior to current production laminates, which have loss tangent values of approximately 0.017.
Due to differential expansion and cure shrinkage of various composite laminate substrate materials during fabrication and use, laminate substrates are non-flat at most temperatures, but may approach a coplanar condition at a single temperature. In particular, laminate substrate silicon chip placement sites, due to high functional wiring density in that location, display strong thermal warpage tendencies over temperature. For best chip assembly yields, it is necessary to control the shape of the chip site during the assembly process. As the temperature of the laminate substrate varies widely during flip chip solder reflow assembly, the shape of the chip site also changes widely. It is necessary to control the shape of the chip site in a non-flat condition to produce a desired range of shapes at solder reflow chip join temperatures for best assembly yields.
Due to CTE mismatch between copper and build-up laminate substrate dielectric material and the usual interconnect structure employed to fan out the signals in a flip chip interconnect, many sequential build-up flip chip laminate substrates are concave at room temperature. These laminates may invert to a convex shape during heating from room to solder reflow temperature. Other laminates may be convex at room temperature and invert to concave with heating. Other laminates may be monotonically concave or convex over the temperature range of interest. The magnitude of warpage varies in all cases. Laminates may be convex over their full area, while a chip site area in the center for single chip laminates may be concave or convex. The shape of the laminate, particularly in the chip site area at soldering temperature, is critical to the joining process. In cases where laminates have cores with thicknesses less than 600 um, or are coreless, a flat chip site shape at joining temperature may be difficult to attain. Existing methods to achieve a flat laminate chip site shape at solder reflow temperature have not been successful.